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A QUAD CMOS GATES CHECKING METHOD

Sergey F. Tyurin

Abstract


The so-called Fault-Tolerant Systems (FTS) use the structural, temporal, functional, or information redundancy for the achievement of the high reliability. For example, Radiation Hardened by Design (RHBD) Systems are Fault-Tolerant Systems. A Passive FTS, due to a very large structural redundancy (Modular Redundancy), produces faults masking. The Triple Modular Redundancy (TMR) Method has more than 300% redundancy. The Quad Redundancy (QR) Method boasts more than 400% redundancy. The CMOS transistors QR (transistor-level redundancy) is the most effective QR. In this case, no voting element is needed. However, this significantly increases the time delay. In addition, it is necessary to ensure compliance with the Mead-Conway restrictions. QR, in contrast to TMR, raises the problem of checking the redundant structure. The author proposes a QR Checking Method based on a selection of substrates of the CMOS transistors. The power lines of the transistor substrates are separated, which ensures the disconnection of part of the reserve. A simulation confirms the feasibility of the proposed method.

Keywords


CMOS Gate; Transistor; Substrate; Reliability; Redundancy; Checking Method.

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References


А. Avizienis, “Fault-tolerant systems,” IEEE Transactions on Computers, vol. C-25, no. 12, pp. 1304-1312, December 1976. [Online]. Available at: https://www.computer.org/csdl/trans/tc/1976/12/01674598.pdf

K. Nørvag, “An Introduction to fault-tolerant systems,” [Online]. Available at: https://www.idi.ntnu.no/~noervaag/papers/IDI-TR-6-99.pdf

P. Balasubramanian, R. T. Naayagi, “Redundant Logic insertion and fault tolerance improvement in combinational circuits,” [Online]. Available at: https://arxiv.org/ftp/arxiv/papers/1707/1707.06909.pdf

Error Detection or Correction of the Data by Redundancy in Hardware (EPO) Patents (Class 714/E11.054). [Online]. Available at: https://patents.justia.com/patents-by-us-classification/714/E11.054

Fault models. [Online]. Available at: https://pdfs.semanticscholar.org/presentation/17fc/d27efe00390a2998fb259b829f4d3efc97e8.pdf

Digital Circuits and the Stuck at Fault Model. [Online]. Available at: https://accendoreliability.com/digital-circuits-stuck-fault-model/

S. Ramaswamy, L. Rockett, D. Patel, et al., “A radiation hardened reconfigurable FPGA,” [Online]. Available at: https://pdfs.semanticscholar.org/57f8/ff540360eadceafc062797b7a01065f6f9cc.pdf

C. Carmichael “Triple module redundancy design techniques for Virtex FPGAs,” [Online]. Available at: https://www.xilinx.com/support/documentation/application_notes/xapp197.pdf

A. H. El-Maleh, A. Al-Yamani, and B. M. Al-Hashimi, “Transistor-level defect tolerant digital system design at the nanoscale,” [Online]. Available at: http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.474.3844&rep=rep1&type=pdf

S.F. Tyurin, “Retention of functional completeness of Boolean functions under “failures” of the arguments,” Automation and Remote Control, vol. 60, no. 9, part 2, pp. 1360-1367, 1999.

W. Weibull, “A statistical distribution function of wide applicability,” [Online]. Available at: https://pdfs.semanticscholar.org/88c3/7770028e7ed61180a34d6a837a9a4db3b264.pdf

C.A. Mead, L. Conway, “Introduction to VLSI systems,” [Online]. Available at: https://www.betterworldbooks.com/product/detail/Introduction-to-VLSI-Systems-9780201043587

PTC Mathcad. [Online]. Available at: https://www.ptc.com/en/products/mathcad/

Use of Triple Modular Redundancy (TMR) Technology in FPGAs, [Online]. Available at: https://www.xilinx.com/support/documentation

Design Techniques for Radiation-Hardened FPGAs, [Online]. Available at: http://application-notes.digchip.com/056/56-39717.pdf

FPGA Design Solution for High-Reliability Applications, [Online]. Available at: https://www.synopsys.com/content/dam/synopsys/implementation&signoff/datasheets/fpga-design-solution-for-high-reliability-applications-brochure.pdf

What is a LUT in FPGA? [Online]. Available at: https://electronics.stackexchange.com/questions/169532/what-is-an-lut-in-fpga

FPGA Architecture White Paper, Altera, [Online]. Available at: https://www.altera.com/en_US/pdfs/literature/wp/wp-01003.pdf

7 Series FPGAs Data Sheet: Overview, [Online]. Available at: https://www.xilinx.com/support/documentation/data_sheets/ds180_7Series_Overview.pdf

A New FPGA Architecture and Leading-Edge FinFET Process Technology Promise to Meet Next-Generation System Requirements, [Online]. Available at: https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/wp/wp-01220-hyperflex-architecture-fpga-socs.pdf

A.V. Grekov, S.F. Tyurin, “Fault tolerant electronic engine controller,” Proceedings of the 2018 IEEE 9th International Conference on Dependable Systems, Services, and Technologies, Kyiv, Ukraine, May 24-27, 2018, pp. 222-224. DOI: 10.1109/DESSERT.2018.8409132


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