Diagnosis of Input Variable Faults of Logical Functions Using Test Map

Authors

  • Vladimir Hahanov
  • Volodymyr Obrizan
  • Svetlana Chumachenko
  • Eugenia Litvinova
  • Hanna Khakhanova
  • Tetiana Borysenko

DOI:

https://doi.org/10.47839/ijc.25.2.4651

Keywords:

in-memory computing, vector logic, fault modeling, circuit diagnosis, simulation modeling

Abstract

This paper introduces a vector-logical mechanism for intelligent computing designed to diagnose non-functional components in models and hardware–software systems. It focuses on detecting faults, defects, destructive modules, embedded trojans, and application activations that produce functional “noise” unrelated to core business processes. The proposed mechanism relies on harmonic interaction between model and algorithm, where the model’s exponential redundancy allows algorithmic nullification of faulty behavior. Two key components of in-memory intelligent computing architecture – modelling and simulation – are analyzed for diagnostic and prognostic tasks. Deterministic models are proposed to perform big-data analysis and classification using a similarity–difference metric, with a truth table serving as an exponentially redundant data structure for energy- and time-efficient processing. An analytical method for solving the covering problem with quadratic computational complexity is presented to generate minimal fault-covering test sets. The proposed method diagnoses all faults in the input variables of RTL, System, and Gate-Level functionality. The study concludes with recommendations for applying this prompt-computing diagnostic approach to improve the reliability and verification of models, software, and hardware systems, supported by practical cloud-based examples using the MOSI service.

References

V. Hahanov, Cyber-Physical Computing for IoT-driven Services, New York: Springer, 2018. 279p. https://doi.org/10.1007/978-3-319-54825-8.

M. Mánik and E. Gramatová, “Efficient diagnostics algorithms for regular computing structures,” Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Cottbus, Germany, 2011, pp. 87-92, https://doi.org/10.1109/DDECS.2011.5783054.

R. Ubar, J. Raik, M. Jenihhin, A. Jutman, Structural Decision Diagrams in Digital Test: Theory and Applications, Birkhäuser Cham, Computer Science Foundations and Applied Logic Series, 1st ed., 2024, XIII+595 pp., ISBN 978-3-031-44733-4 (hardcover), ISBN 978-3-031-44736-5 (softcover), ISBN 978-3-031-44734-1 (eBook). https://doi.org/10.1007/978-3-031-44734-1.

S. Zhu, T. Yu, T. Xu, H. Chen, S. Dustdar, S. Gigan, D. Gunduz, E. Hossain, Y. Jin, F. Lin, B. Liu, Z. Wan, J. Zhang, Z. Zhao, W. Zhu, Z. Chen, T. S. Durrani, H. Wang, J. Wu, T. Zhang, Y. Pan, “Intelligent computing: The latest advances, challenges, and future,” Intelligent Computing, vol. 2, article ID: 0006, 2023. https://doi.org/10.34133/icomputing.0006.

M. Abdulmaksoud, N. Dehadrai, J. Castrillón, A. Sakr and R. Schuster, “Edge diagnostics platform: Orchestration and diagnosis model for edge computing infrastructure,” Proceedings of the 2021 IEEE International Conference on Edge Computing (EDGE), Chicago, IL, USA, 2021, pp. 51-59, https://doi.org/10.1109/EDGE53862.2021.00017.

H. R. H. Al-Absi, A. Abdullah and M. I. Hassan, “Soft computing in medical diagnostic applications: A short review,” Proceedings of the 2011 National Postgraduate Conference, Perak, Malaysia, 2011, pp. 1-5, https://doi.org/10.1109/NatPC.2011.6136288.

S. Kaur and E. K. Lee, “Diagnostic analysis: Directional relation graph,” Proceedings of the 2019 IEEE International Conference on Cluster Computing (CLUSTER), Albuquerque, NM, USA, 2019, pp. 1-5, https://doi.org/10.1109/CLUSTER.2019.8891032.

J. Xu, S. Guo, H. Guo and X. Tian, “A novel diagnostic method for single and dual power switch open-circuit faults of six-phase FTPMSM system even in fault tolerant operation,” IEEE Transactions on Power Electronics, vol. 37, no. 8, pp. 9777-9789, 2022, https://doi.org/10.1109/TPEL.2022.3161437.

X. Zhao, P. Jiang and L. Liu, “Research of parallel scheduling strategy for hierarchical SiP test using IEEE 1500 standard,” Proceedings of the 2014 15th International Conference on Electronic Packaging Technology, Chengdu, China, 2014, pp. 1108-1111, https://doi.org/10.1109/ICEPT.2014.6922838.

G. Ali, F. A. Hussin, N. B. Z. Ali and N. H. Hamid, “Enhancement in IEEE 1500 standard for at-speed functional testing,” Proceedings of the 2014 5th International Conference on Intelligent and Advanced Systems (ICIAS), Kuala Lumpur, Malaysia, 2014, pp. 1-5, https://doi.org/10.1109/ICIAS.2014.6869507.

P. Inglese, E.-I. Vatajelu and G. Di Natale, “Side channel and fault analyses on memristor-based logic in-memory,” IEEE Design & Test, vol. 41, no. 3, pp. 29-35, 2024, https://doi.org/10.1109/MDAT.2023.3324522.

D. Gajaria, K. A. Gomez and T. Adegbija, “STT-RAM-based hierarchical in-memory computing,” IEEE Transactions on Parallel and Distributed Systems, vol. 35, no. 9, pp. 1615-1629, 2024, https://doi.org/10.1109/TPDS.2024.3430853.

M. Zhang, A. Lebeck and D. Sorin, “Fractal consistency: Architecting the memory system to facilitate verification,” IEEE Computer Architecture Letters, vol. 9, no. 2, pp. 61-64, 2010, https://doi.org/10.1109/L-CA.2010.18.

R. Ben Fekih, M. Lahami, S. Bradai and M. Jmaiel, “Formal verification of ERC-based smart contracts: A systematic literature review,” IEEE Access, vol. 13, pp. 11396-11422, 2025, https://doi.org/10.1109/ACCESS.2025.3527158.

W. Chen, S. Ray, J. Bhadra, M. Abadir and L.-C. Wang, “Challenges and trends in modern SoC design verification,” IEEE Design & Test, vol. 34, no. 5, pp. 7-22, 2017, https://doi.org/10.1109/MDAT.2017.2735383.

A. Kamput, C. Dechsupa, W. Vatanawood and S. Pomsiri, “Scalable timed-automata models for traffic light control systems: Challenges and solutions in formal verification,” IEEE Access, vol. 12, pp. 124260-124281, 2024, https://doi.org/10.1109/ACCESS.2024.3455097.

I. Pomeranz, “Computation of seeds for LFSR-based diagnostic test generation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 12, pp. 2004-2012, 2015, https://doi.org/10.1109/TCAD.2015.2459031.

I. Pomeranz, “Diagnostic test generation that addresses diagnostic holes,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no. 2, pp. 335-344, 2019, https://doi.org/10.1109/TCAD.2018.2812121.

I. Pomeranz, S. M. Reddy and S. Venkataraman, “z-Diagnosis: A framework for diagnostic fault simulation and test generation utilizing subsets of outputs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 9, pp. 1700-1712, 2007, https://doi.org/10.1109/TCAD.2007.895758.

I. Pomeranz, “Low-power diagnostic test sets for transition faults based on functional broadside tests,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 11, pp. 2428-2432, 2014, https://doi.org/10.1109/TVLSI.2013.2290768.

X. Wu, R. Tian, S. Cheng, T. Chen and L. Tong, “A nonintrusive diagnostic method for open-circuit faults of locomotive inverters based on output current trajectory,” IEEE Transactions on Power Electronics, vol. 33, no. 5, pp. 4328-4341, 2018, https://doi.org/10.1109/TPEL.2017.2711598.

J. Liu et al., “Open-circuit fault diagnosis strategy for five-phase permanent magnet fault-tolerant servo motor drive systems based on phase voltage,” IEEE Transactions on Industry Applications, vol. 61, no. 3, pp. 3612-3622, 2025, https://doi.org/10.1109/TIA.2025.3532912.

S. Zhou, Z. Chen and T. Lin, “Lithium-ion battery cell open circuit fault diagnostics: methods, analysis, and comparison,” IEEE Transactions on Power Electronics, vol. 38, no. 2, pp. 2493-2505, 2023, https://doi.org/10.1109/TPEL.2022.3211568.

Y. Hu, S. Cheng, X. Wu, C. Xiang and Z. Li, “A diagnostic method for open-circuit faults of loads and semiconductors in 3L-NPC inverters,” IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 11, no. 3, pp. 2577-2590, 2023, https://doi.org/10.1109/JESTPE.2022.3205897.

I. Pomeranz, “RETRO: Reintroducing tests for improved reverse order fault simulation,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 8, pp. 1930-1934, 2020, https://doi.org/10.1109/TVLSI.2020.2997762.

P. Wang, A. M. Gharehbaghi and M. Fujita, “An automatic test pattern generation method for multiple stuck-at faults by incrementally extending the test patterns,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 10, pp. 2990-2999, 2020, https://doi.org/10.1109/TCAD.2019.2957364.

L. Anghel, R. Cantoro, R. Masante, M. Portolan, S. Sartoni and M. S. Reorda, “Self-test library generation for in-field test of path delay faults,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 42, no. 11, pp. 4246-4259, 2023, https://doi.org/10.1109/TCAD.2023.3268210.

V. Hahanov et al., “Prompt-testing of logic,” Proceedings of the 2024 IEEE East-West Design & Test Symposium (EWDTS), Yerevan, Armenia, 2024, pp. 1-5, https://doi.org/10.1109/EWDTS63723.2024.10873774.

D. Devadze et al., “In-memory fault-free vector simulation,” Proceedings of the 2023 IEEE East-West Design & Test Symposium (EWDTS), Batumi, Georgia, 2023, pp. 1-6, https://doi.org/10.1109/EWDTS59469.2023.10297076.

V. Hahanov, V. Obrizan, I. Hahanova and E. Fomina, “Verification of digital system by a new asserting mechanism based on IEEE 1500 sect standard,” Proceedings of the International Conference Mixed Design of Integrated Circuits and System, MIXDES 2006, Gdynia, Poland, 2006, pp. 544-548, https://doi.org/10.1109/MIXDES.2006.1706639.

Y. Zheng, G. Shcherbakova, B. Rusyn, A. Sachenko, N. Volkova, I. Kliushnikov, S. Antoshchuk, “Wavelet transform cluster analysis of UAV images for sustainable development of smart regions due to inspecting transport infrastructure,” Sustainability, vol. 17, issue 3, 927, 2025. https://doi.org/10.3390/su17030927.

Downloads

Published

2026-06-30

How to Cite

Hahanov, V., Obrizan, V., Chumachenko, S., Litvinova, E., Khakhanova, H., & Borysenko, T. (2026). Diagnosis of Input Variable Faults of Logical Functions Using Test Map. International Journal of Computing, 25(2), 253-261. https://doi.org/10.47839/ijc.25.2.4651

Issue

2026, Volume 25, Issue 2

Section

Articles

License

International Journal of Computing is an open access journal. Authors who publish with this journal agree to the following terms:
•    Authors retain copyright and grant the journal right of first publication with the work simultaneously licensed under a Creative Commons Attribution License that allows others to share the work with an acknowledgement of the work's authorship and initial publication in this journal.
•    Authors are able to enter into separate, additional contractual arrangements for the non-exclusive distribution of the journal's published version of the work (e.g., post it to an institutional repository or publish it in a book), with an acknowledgement of its initial publication in this journal.
•    Authors are permitted and encouraged to post their work online (e.g., in institutional repositories or on their website) prior to and during the submission process, as it can lead to productive exchanges, as well as earlier and greater citation of published work.