DETECTION METHOD OF THE PROBABLE INTEGRITY VIOLATION AREAS IN FPGA-BASED SAFETY-CRITICAL SYSTEMS
Keywords:LUT-oriented architecture, FPGA, hardware Trojans, safety-critical systems, integrity monitoring.
AbstractThe features of integrity monitoring of FPGA-based safety-critical systems are considered. Hardware Trojans are distinguished as one of the most dangerous types of malicious integrity violation of FPGA-based systems. The study has proved that Hardware Trojans can be implanted into the system (or system project) during its planned modification. In particular, it happens when the integrity monitoring, based on the hash sum usage, does not operate. Before running the integrity monitoring, one should ensure that Hardware Trojans were not implanted. Authors proposed the method for detecting the hardware Trojans location in the space of FPGA-based components of safety-critical systems. The method is based on the analysis of addressing to the values of calculated LUT units for these components in the normal and emergency modes of system operation. The hardware module for addressing the registration in accordance with the proposed method is implemented.
G. Xie, Y. Chen, R. Li, K. Li, “Hardware Cost Design Optimization for Functional Safety-Critical Parallel Applications on Heterogeneous Distributed Embedded Systems,” IEEE Transactions on Industrial Informatics, vol. 14, no. 6, pp. 2418-2431, 2018. DOI: 10.1109/TII.2017.2768075.
C. Cho, W. Chung, S. Kuo, “Using Tree-Based Approaches to Analyze Dependability and Security on I&C Systems in Safety-Critical Systems,” IEEE Systems Journal, vol. 12, no. 2, pp. 1118-1128, 2018. DOI: 10.1109/JSYST.2016.2635681
C. Unsalan, B. Tar, Digital System Design with FPGA, McGraw-Hill, 2017, 402 p.
F. Kastensmidt, P. Rech (Eds.), FPGAs and Parallel Architectures for Aerospace Applications: Soft Errors and Fault-Tolerant Design, Springer, Cham, Switzerland, 2016, 325 p.
R. Woods, J. McAllister, G. Lightbody Y. Yi, FPGA-based Implementation of Signal Processing Systems, 2nd Edition, Wiley, Hoboken, USA, 2017, 356 p.
J. Andina, FPGAs: Fundamentals, Advanced Features, and Applications in Industrial Electronics, CRC Press, Boca Raton, USA, 2017, 266 p.
A. Avizienis, J. Laprie, B. Randell, C. Landwehr, “Basic Concepts and Taxonomy of Dependable and Secure Computing,” IEEE Transactions on Dependable and Secure Computing, vol. 1, issue 1, pp. 11-33, 2004.
D. Maevsky, E. Maevskaya, L. Shapa, “Software reliability growth model’s assumptions in context of the secondary faults,” CEUR Workshop Proceedings, vol. 1844, pp. 645-653б 2017.
N. Sklavos, R. Chaves, G. Natale, F. Regazzoni (Eds.), Hardware Security and Trust: Design and Deployment of Integrated Circuits in a Threatened Environment, Springer, Cham, Switzerland, 2017, 254 p.
L. Bossuet, L. Torres (Eds.), Foundations of Hardware IP Protection, Springer, New-York, USA, 2018, 248 p.
H. Salmani, M. Tehranipoor, “Analyzing circuit vulnerability to hardware Trojan insertion at the behavioral level,” Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), New York, USA, 2013, pp. 190-195.
D. Kleidermacher, M. Kleidermacher, Embedded Systems Security: Practical Methods for Safe and Secure Software and Systems Development, Newnes. Boston, USA, 2012, 416 p.
M. Bishop, Computer Security, 2nd Edition, Addison-Wesley, Boston, USA, 2018, 1440 p.
O. Kehret, A. Walz, A. Sikora, “Integration of Hardware Security Modules into a Deeply Embedded TLS Stack,” International Journal of Computing, vol. 15, issue 1, pp. 22-30, 2016.
M. Tehranipoor, H. Salmani, X. Zhang, Integrated Circuit Authentication: Hardware Trojans and Counterfeit Detection, Springer, Cham, 2013, 224 p.
A. Adetomi, G. Enemali, T. Arslan, “Relocating Encrypted Partial Bitstreams by Advance Task Address Loading,” Proceedings of the IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Napa, CA, 2017, pp. 188-191. DOI: 10.1109/FCCM.2017.50
J. Katz, Y. Lindell, Introduction to Modern Cryptography, Second Edition, Chapman & Hall/CRC, 2014, 604 p.
D. Grochol, L. Sekanina, “Fast reconfigurable hash functions for network flow hashing in FPGAs,” Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Edinburgh, 2018, pp. 257-263. DOI: 10.1109/AHS.2018.8541401.
W. Stallings, Cryptography and Network Security: Principles and Practice, 7th Edition, Pearson Education Limited, Harlow, United Kingdom, 2017, 768 p.
J. Katz, Digital Signatures. Advances in Information Security, Springer, New York, USA, 2010, 192 p.
K. Zashcholkin, O. Ivanova, “LUT-object integrity monitoring methods based on low impact embedding of digital watermark,” in Proceedings of the 14th International Conference “Advanced Trends in Radioelecrtronics, Telecommunications and Computer Engineering (TCSET-2018)”, Lviv-Slavske, Ukraine, 2018, pp. 519-523.
F. Shih, Digital Watermarking and Steganography: Fundamentals and Techniques, 2nd Edition, CRC Press, Boca Raton, USA, 2017, 292 p.
IEC 61508:2010 “Functional Safety of Electrical / Electronic / Programmable Electronic Safety-related Systems”, 2010.
J. Kim, E.-S. Kim, J. Yoo, Y. J.Lee, J.-G. Choi, “An integrated software testing framework for FPGA-based controllers in nuclear power plants,” Nuclear Engineering and Technology, vol. 48, issue 2, pp. 470-481, 2016.
E.-S. Kim, D.-A. Lee, S. Jung, J. Yoo, J.-G. Choi, J.-S. Lee, “NuDE 2.0: A formal method-based software development, verification and safety analysis environment for digital I&Cs in NPPs.” Journal of Computing Science and Engineering, vol. 11, issue 1, pp. 9-23, 2017. DOI: 10.5626/JCSE.2017.11.1.9.
K. Zashcholkin, O. Drozd, “The detection method of probable areas of hardware trojans location in FPGA-based components of safety-critical systems,” Proceedings of the IEEE 9th International Conference on Dependable Systems, Services and Technologies DESSERT-2018, Kiev, Ukraine, 2018, pp. 220-225.
R. Chakraborty, I. Saha, A. Palchaudhuri, G. Naik, “Hardware trojan insertion by direct modification of FPGA configuration bitstream,” IEEE Design & Test, vol. 30, no. 2, pp. 45-54, 2013. DOI: 10.1109/MDT.2013.2247460.
M. Komar, V. Golovko, A. Sachenko, S. Bezobrazov, “Development of neural network immune detectors for computer attacks recognition and classification,” Proceedings of the 7th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications IDAACS’2019, Berlin, Germany, 12-14 September 2013, pp. 665-668.
T. Zhang and X. Wang, “High-reliable testing for FPGA software in space utilization engineering,” Proceedings of the International Conference on Dependable Systems and their Applications (DSA), Beijing, 2017, pp. 86-91. DOI: 10.1109/DSA.2017.22.
H. Amano, Principles and Structures of FPGAs, Springer, 2018, 232 p.
O. Drozd, M. Kuznietsov, O. Martynyuk, M. Drozd, “A method of the hidden faults elimination in FPGA projects for the critical applications,” Proceedings of the 9th IEEE International Conference on Dependable Systems, Services and Technologies (DESSERT’2018), Kyiv, Ukraine, 2018, pp. 231–234. DOI: 10.1109/DESSERT.2018.8409131.
T. Xu, H. Wang, T. Yuan, M. Zhou, “BDD-Based synthesis of fail-safe supervisory controllers for safety-critical discrete event systems,” IEEE Transactions on Intelligent Transportation Systems, vol. 17, no. 9, pp. 2385-2394, 2016. DOI: 10.1109/TITS.2016.2515063
V. Piterska, O. Kolesnikov, D. Lukianov, K. Kolesnikova, V. Gogunskii, T. Olekh, A. Shakhov, S. Rudenko, “Development of the Markovian model for the life cycle of a project’s benefits,” Eastern-European Journal of Enterprise Technologies, vol. 5, no. 4 (95), pp. 30-39, 2018. DOI:10.15587/1729-4061.2018.145252.
A. Drozd, S. Antoshchuk, J. Drozd, K. Zashcholkin, M. Drozd, M. Kuznietsov, M. Al-Dhabi, V. Nikul, Checkable FPGA Design: Energy Consumption, Throughput and Trustworthiness, in: V. Kharchenko, Y. Kondratenko, J. Kacprzyk (Eds.), Green IT Engineering: Social, Business and Industrial Applications, Studies in Systems, Decision and Control, vol. 171, Springer International Publishing, Berlin, Heidelberg, 2019, pp. 73-94. DOI: 10.1007/978-3-030-00253-4_4.
Y. Kondratenko, S. Encheva, E. Sidenko, “Synthesis of intelligent decision support systems for transport logistic,” Proceedings of the 6th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications, IDAACS’2011, Prague, Czech Republic, 2011, vol. 2, pp. 642-646. DOI: 10.1109/IDAACS.2011.6072847.
Intel Quartus, [Online]. Available at: https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/overview.html.
Intel Cyclone FPGA series, [Online]. Available: https://www.intel.com/content/www/us/en/products/programmable/cyclone-series.html.
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