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A FLEXIBLE IMAGE PROCESSING DESIGN BASED ON 2D DCT/IDCT FOR A SYSTEM ON A PROGRAMMABLE CHIP

Mohamed Atri, Wajdi Elhamzi, Rached Tourki

Abstract


Many multimedia applications require a flexible image pr ocessing architecture. In this paper, we present the use of a hardware acceleration module (Discrete Cosine Transform (DCT) and Inverse DCT (IDCT) coupled with a software partition running on a PowerPC Processor of a Xilinx FPGA. Therefore we have the benefits of flexible software partition on the PowerPC and the acceleration given by the remaining logic of the same FPGA. This implementation can be used in the context of video coding, object recognition, etc. The experimental results show optimization in processing time offered by hardware acceleration vs. software implementation.

Keywords


System on Programmable Chip; 2D-DCT/IDCT; Xilinx FPGA; Embedded Processor; Image Processing.

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References


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