CODE COMPRESSION FOR THE EMBEDDED ARM/THUMB PROCESSOR

Authors

  • Xianhong Xu
  • Simon Jones

DOI:

https://doi.org/10.47839/ijc.3.2.279

Keywords:

ARM, THUMB, Memory, Code, Compression

Abstract

Previous code compression research on embedded systems was based on typical RISC instruction code. THUMB from ARM Ltd is a compacted 16-bits instruction set showing a great code density than its original 32-bits ARM instruction. Our research shows that THUMB code is compressible and a further 10-15% code size reduction on THUMB code can be expected using our proposed new architecture – Code Compressed THUMB Processor. In our proposal, Level 2 cache or additional RAM space is introduced to serve as the temporary storage for decompressed program blocks. A software implementation of the architecture is proposed and we have implemented a software prototype based on ARM922T processor, which runs on the ARMulator.

References

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Published

2014-08-01

How to Cite

Xu, X., & Jones, S. (2014). CODE COMPRESSION FOR THE EMBEDDED ARM/THUMB PROCESSOR. International Journal of Computing, 3(2), 7-12. https://doi.org/10.47839/ijc.3.2.279

Issue

2004, Volume 3, Issue 2

Section

Articles

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