FAULT TOLERANT MEMORY SYSTEM WITH ACTIVE REDUNDANCY FOR CRITICAL APPLICATIONS

Authors

  • Petru Cascaval
  • Doina Cascaval

DOI:

https://doi.org/10.47839/ijc.4.1.328

Keywords:

BIST-RAM, Online Testing, Fault Tolerance, Reliability, Safety, Reconfigurable System

Abstract

This paper proposes a fault tolerant RAM memory architecture with active redundancy dedicated to critical applications. To assure high reliability, additional modules are provided in the system. To reach a high safety, memory system is composed by built-in self-testing RAM devices (BIST?RAM). Memory modules are tested online one by one, in a sequential order, during the normal operation. A primary module under testing is temporary replaced by another one. If one module is diagnosed as being failed it is eliminated from the system automatically and replaced with a spare module. The memory control unit responsible for performing the reconfiguration of the memory system has a cellular structure and introduces an acceptable extra delay for the memory access.

References

D. Pradhan, Fault-Tolerant Computer System Design, Prentice Hall, New York (1996).

H. Al–Asaad, B. Murray, J. Hayes, Online BIST for Embedded Systems, IEEE Design & Test of Computers, 15 (4), (1998), pp.17-24.

S. Barbagallo, et al., Integrating Online and Offline Testing of a Switching Memory, IEEE Design & Test of Computers, 15 (1) (1998), pp. 63-70.

M. Lobetti – Bodoni, A. Pricco, et al., An On-Line Bisted SRAM IP Core, Digest of Papers, Int'l Test Conference, Washington, (1999), pp. 993-999.

P. Cascaval, S. Bennett, Efficient March Test for 3-Coupling Faults in Random Access Memories, J. of Microprocessors and Microsystems, Elsevier, 24 (10) (2001), pp. 501-509.

P. Cascaval , V. Onofrei., Built-in Self-Testing for Coupling Faults in Random Access Memories, Bul. Inst. Polit.Iasi, XLVI (L), 1-4, Autom. Control & Computer Science., (2000), pp. 93-101.

P. Cascaval, New results in testing of microprocessor based systems, PhD Diss., Tech. Univ."Gh.Asachi", Iassy, (2001), pp. 162-170.

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Published

2014-08-01

How to Cite

Cascaval, P., & Cascaval, D. (2014). FAULT TOLERANT MEMORY SYSTEM WITH ACTIVE REDUNDANCY FOR CRITICAL APPLICATIONS. International Journal of Computing, 4(1), 80-86. https://doi.org/10.47839/ijc.4.1.328

Issue

2005, Volume 4, Issue 1

Section

Articles

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