INVESTIGATION OF CARRIER MOBILITY DEGRADATION EFFECTS ON MOSFET LEAKAGE SIMULATIONS

Authors

  • Hippolyte Djonon Tsague
  • Bhekisipho Twala

DOI:

https://doi.org/10.47839/ijc.15.4.855

Keywords:

electron mobility, transconductance, strain silicon, hole mobility, semiconductor, transistor, leakage, simulation.

Abstract

The term carrier mobility generally alludes to both electron and hole mobility in semiconductors. These parameters characterize how quickly an electron and/or hole moves through a metal or semiconductor when under the influence of an electric field. Most studied mobility models only take into account the influence of temperature and doping concentration which provides less accurate but faster simulation and allows preliminary device description adjustments and analysis. However complete models, like Klaassen, Shirahata or some allowed model combination give results that better fit experimental curves. This work focuses on such possibilities and shows that, as carriers are accelerated in an electric field, their velocity will begin to saturate when the electric field magnitude becomes significant. Such effects are observed in low, high and inversion mobility models simulated in strain-Silicon devices. These effects are to be accounted for by reducing of the effective mobility. Furthermore, it is shown that charge carriers in semiconductors are electrons and holes and that, their numbers are controlled by the concentrations of impurity elements, i.e. doping concentration; for that reason doping concentration has great influence on carrier mobility. Carriers are able to flow more quickly in materials with higher mobility; since the speed of an embedded device is limited by the time it takes a carrier to move from one side to the other. Devices composed of materials with higher mobility are able to achieve higher speeds.

References

A. Sabnis, and J. T. Clemens, “Characterization of the Electron Mobility in the inverted range Si Surface,” IEDM Tech., Dig. 1979, Vol. 25, pp. 18-21, 1979.

J. P. Colinge, and C. A Colinge, Physics of Semiconductor Devices, Springer Verlag, NY, 2002.

H. D. Tsague and B. Twala, “First principle leakage current reduction technique for CMOS devices,” in Proceedings of the International Conference on Computing, Communication and Security (ICCCS’2015), Port Louis, Mauritius, 2015.

D. M. Caughey, and R. E. Thomas, “Carrier Mobilities in Silicon Empirically Related to Doping and Field,” in Proceedings of the IEEE, Vol. 55, No. 12, pp. 2192-2193, 1967.

C. Cassi and B. Ricco, “An Analytical Model of the Energy Distribution of Hot Electrons,” IEEE Transactions on Electron Devices, Vol. 37, Issue 6, pp. 1514-1521, 1990.

K. Balakrishnan et. al, “Measurement and analysis of gate-induced drain leakage in short-channel strained silicon germanium-on-insulator p-MOS FinFETs,” in Proceedings of the 72nd Device Research Conference, 2014, pp. 183-184.

P. Damas, X. Le-Roux, D. Marris-Morini, E. Cassan, L. Vivien “Strained silicon for photonics applications,” in Proceedings of the 17th International Conference on Transparent Optical Networks (ICTON), 5-9 July 2015, pp. 1.

M. Ray, A. Jana, U. Ghanta, N. Ratan, “Photoluminescence from Oxidized Macroporous Silicon: Nanoripples and Strained Silicon Nanostructures,” IEEE Transactions on Device and Materials Reliability, Vol. 13, Issue 1, pp. 87-92, 2013.

S. Richter, C. Sandow, A. Nichau, S. Trellenkamp, M. Schmidt, R. Luptak, K. K. Bourdelle, Q. T. Zhao, S. Mantl, “Gated Silicon and Strained Silicon Nanowire Array Tunneling FETs,” IEEE Electron Device Letters, Vol. 33, Issue 11, pp. 1535-1537, Sep. 2012.

J. C. Tinoco, J. Alvarado, A. G. Martinez-Lopez, B. Iñiguez, A. Cerdeira, “Drain current model for bulk strained silicon NMOSFETs,” in Proceedings of the IEEE 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS), 2012, pp. 1-4.

J. B. Roldán, F. Gámiz, P. Cartujo-Cassinello, P. Cartujo, J. E. Carceller, and A. Roldan, “Strained-Si on Si1-x Gex MOSFET Mobility Model,” IEEE Transactions on Electron Devices, Vol. 50, No. 5, pp. 1408-1411, May 2003.

Z. Yang, Z. Dawei and T. Lilin, “An improved Strained-Si on Si1-xGex MOSFET Mobility Model,” IEEE, Vol. 2, pp. 1216-1219, 2004.

M. H. Bhuyan, and Q. D. M. Khosru, “Inversion Layer Effective Mobility Model for Pocket Implanted Nano Scale n-MOSFET,” International Journal of Electrical and Electronics Engineering, Vol. 5, Issue 1, pp. 1-8, 2011.

International Technology Roadmap for Semiconductors, Semiconductor Industry Association, San Jose, 2011.

T. K. Maiti, A. Banerjee, C. K. Maiti, “An Explicit Surface-Potential Based Biaxial Strained-Si n-MOSFET Model for Circuit Simulation,” Journal of Scientific Research, Vol. 2, No. 11, pp. 879-887, 2016.

C. K. Maiti, S. Chattopadhyay and L. K. Bea, Strained-Si Hetero-structure Field Effect Device, Taylor & Francis Group LLC, Boca Raton, 2007.

C. K. Maiti and G. A. Armstrong, Applications of Silicon-Germanium Hetero-structure Devices, Institute of Physics Publisher, Bristol, 2001.

J. L. Hoyt, H. M. Nayfeh, S. Eguchi, I. Aberg, G. Xia, T. Drake, E. A. Fitzgerald and D. A. Antoniadis, “Strained Silicon MOSFET Technology,” IEEE International Electron Devices Meeting Technical Digest, San Francisco, 8-11 December 2002, pp. 23-26.

R. W. Keyes, “Explaining Strain in Silicon,” IEEE Circuits & Devices Magazine, Vol. 35, pp. 36-39, 2002.

J. Welser, J. L. Hoyt, S. Takagi and J. F. Gibbons, “Strain Dependence of the Performance Enhancement in Strained-Si n-MOSFETs,” IEEE International Electron Devices Meeting Technical Digest, San Francisco, 11-14 December 1994, pp. 373-376.

H. D. Tsague and B. Twala, “Simulation and Parameter Optimization of Polysilicon Gate Biaxial Strained Silicon MOSFETs,” in Proceedings of the 5th International Conference on Digital Information Processing and Communications, ICDIPC, Switzerland 2015.

ATLAS User’s Manual, Santa Clara, CA: Silvaco International, April 1997.

C. K. Maiti, L. K. Bera and S. Chattopadhyay, Strained-Si Heterostructure Field Effect Transistors,” Semiconductor Science and Technology, Vol. 13, No. 11, 1998, pp. 1225-1246.

J. Welser, J. L. Hoyt and J. F. Gibbons, “Electron Mobility Enhancement in Strained-Si N-Type Metal-Oxide-Semiconductor Field-Effect Transistors,” IEEE Electron Device Letters, Vol. 15, No. 3, pp. 100-102, 1994.

D. K. Nayak, J. C. S. Woo, J. S. Park, K. L. Wang and K. P. Macwilliams, “High-Mobility p-Channel Metal-Oxide-Semiconductor Field-Effect Transistor on Strained Si,” Applied Physics Letters, Vol. 62, No. 22, pp. 2853-2855, 1993.

S. Takagi, A. Toriumi, M. Iwase, H. Tango, “On the universality of inversion layer mobility in Si MOSFET's: Part I-Effects of substrate impurity concentration,” IEEE Transactions on Electron Devices, Vol. 41, pp. 2357-2362, 1994.

Y. J. Wong, I. Saad, R. Ismail, “Characterisation of Strained Silicon MOSFET Using Semiconductor TCAD Tools,” in Proceedings of the ICSE’2006, Kuala Lumpur, 2006.

D. Vasilesca, “Mobility Modelling,” available online http://manualzz.com/doc/6506074/mobility-modeling (Last visited Dec. 13, 2016).

Electron mobility, Wikipedia contributor, https://en.wikipedia.org/w/index.php?title=Electron_mobility&oldid=751100975 (Last visited Nov. 23, 2016).

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Published

2016-12-29

How to Cite

Tsague, H. D., & Twala, B. (2016). INVESTIGATION OF CARRIER MOBILITY DEGRADATION EFFECTS ON MOSFET LEAKAGE SIMULATIONS. International Journal of Computing, 15(4), 237-247. https://doi.org/10.47839/ijc.15.4.855

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