A METHOD OF PREDICTING THE MAINTENANCE PERIOD OF EMBEDDED SYSTEMS FOR PREVENTING BREACH OF THEIR TIME REQUIREMENTS
Keywords:real-time embedded system, predicting maintenance period, firmware execution time, hardware aging.
AbstractThe work deals with a significant problem of ensuring that the execution time of a firmware running inside a microcontroller-based real-time embedded system never goes out of its expected range, no matter for how long the embedded system has been used. Once having been tested before the first usage, a newly created embedded system is gradually getting slower in its response, due to the fact that its hardware components get worn-out with aging. A possible solution is a replacement of the hardware components that most contribute to such a change in the response time of the embedded system. If such a replacement takes place too far in advance, long before hardware components actually start showing any decline in their response time, the above-mentioned solution is cost-ineffective and impractical, as it leads to a waste of equipment and efforts. We introduce a method for predicting the appropriate maintenance period of a real-time embedded system on the basis of the characteristics of its hardware components.
J. Stankovic, “Misconceptions about real-time computing: a serious problem for next generation systems,” Computer, Vol. 21, Issue 10, pp. 10-19, 1988. DOI: 10.1109/2.7053
T. K. Ferrel, U. D. Ferrel, RTCA DO-178B/EUROCAE ED-12B, Ferrell and Associates Consulting.
ARINC 653 - An Avionics Standard for Safe, Partitioned Systems. Wind River Systems, IEEE Seminar, 2008.
V. Kharchenko, Y. Ponochovnyi, A.-S. M. Q. Abdulmunem and A. Boyarchuk, “Security and availability models for smart building automation systems”, International Journal of Computing, Vol. 16, Issue 4, pp. 194-202, 2017.
X. Li, A. Roychoudhury, T. Mitra, “Modeling out-of-order processors for software timing analysis,” in Proceedings of the 25th IEEE Real-Time Systems Symposium (RTSS’04), Libon, December 5-8, 2004, pp. 92-103. DOI: 10.1109/REAL.2004.33.
J. Souyris, E. Pavec, G. Himbert, “Computing the worst-case execution time of an avionics program by abstract interpretation,” in Proceedings of the 5th International Workshop on Worst-Case Execution Time Analysis, (WCET’2005), Palma de Mallorca, July 5, 2005, pp. 55-59. DOI:10.4230/OASIcs.WCET.2005.810.
C. Ferdinand, R. Heckmann, H. Theiling, “Convenient user annotations for a WCET tool,” in Proceedings of the 3-rd International Workshop on Worst-Case Execution Time Analysis, (WCET’2003), Porto, July 1, 2003. pp. 17–20.
J. Engblom Processor Pipelines and Static Worst-Case Execution Time Analysis: Ph.D. thesis / J. Engblom – Uppsala: Uppsala University, 2002. ISBN 91-554-5228-0.
C. Healy, R. Arnold, F. Muller, “Bounding pipeline and instruction cache performance,” IEEE Transactions on Computers, Vol. 48, Issue 1, pp. 53-70, 1999. DOI: 10.1109/12.743411.
P. Atanassov, R. Kirner, P. Puschner, “Using real hardware to create an accurate timing model for execution-time analysis,” in Proceedings of the IEEE Real-Time Embedded Systems Workshop, held in conjunction with (RTSS'2001), 2001.
D. Stewart, “Measuring execution time and real-time performance,” in Proceedings of the Embedded Systems Conference (ESCSF), San Francisco, 2004.
Y. Zhang, Evaluation of methods for dynamic time analysis for CC systems AB, Thesis of Master’s degree, Vasteras, Malardalen University, 2005.
M. Wahler, E. Ferranti, R. Steiger, R. Jain, “CAST: automating software tests for embedded systems,” in Proceedings of the 15th International Conference on Software Testing, Verification and Validation, April 17-21, 2012, pp. 123-133. DOI: 10.1109/ICST.2012.126.
R. Chopey, B. Knysh, D. Fedasyuk, “The model of software execution time remote testing,” in Proceedings of the 9th International Conference of Young Scientists «Computer Science and Engineering 2017» (CSE’2017), Lviv, 2017, pp. 398–402.
R. Kirner, “The WCET Analysis Tool CalcWcet167,” in Proceedings of the 5th International Symposium on Leveraging Applications of Formal Methods, Verification and Validation. Applications and Case Studies, October 15-18, 2012, pp. 158-172. DOI: 10.1007/978-3-642-34032-1_17.
D. Fedasyuk, R. Chopey, B. Knysh, “Architecture of a tool for automated testing the worst-case execution time of real-time embedded systems' firmware,” in Proceedings of the 14th International Conference of Experience of Designing and Application of CAD Systems in Microelectronics (CADSM), Lviv, February 21-25, 2017, pp. 278–282. DOI: 10.1109/CADSM.2017.7916134
J. Engblom, F. Stappert, A. Ermedahl, “Structured testing of worst-case execution time analysis tools,” in Proceedings of the 21st Real-Time System Symposium (RTSS/WIP’00), Orlando, November 27-30, 2000, pp. 154–163.
U.S. Nuclear Regulatory Commission, Effect of Aging on Response Time of Nuclear Plant Pressure Sensors, Washington DC, 1989.
ADS1118 Ultrasmall, Low-Power, SPI™-Compatible, 16-Bit Analog-to-Digital Converter with Internal Reference and Temperature Sensor. Texas Instruments, 2013.
AT45DB041E 4-Mbit DataFlash SPI Serial Flash Memory. Adesto Technologies, 2013.
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